High-Speed Digital System Design

мај 2022 г. · Springer Nature

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High-Speed Digital System Design bridges the gap from theory to implementation in the real world. Systems with clock speeds in low megahertz range qualify for high-speed. Proper design results in quality digital transmissions and lowers the chance for errors. This book is for computer and electrical engineers who may or may not have learned electromagnetic theory. The presentation style allows readers to quickly begin designing their own high-speed systems and diagnosing existing designs for errors. After studying this book, readers will be able to: Design the power distribution system for a printed circuit board to minimize noise Plan the layers of a PCB for signals, power, and ground to maximize signal quality and minimize noise Include test structures in the printed circuit board to easily diagnose manufacturing mistakes Choose the best PCB design parameters such a trace width, height,and routed path to ensure the most stable characteristic impedance Determine the correct termination to minimize reflections Predict the delay caused by a given PCB trace Minimize driver power consumption using AC terminations Compensate for discontinuities along a PCB trace Use pre-emphasis and equalization techniques to counteract lossy transmission lines Determine the amount of crosstalk between two traces Diagnose existing PCBs to determine the sources of errors

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Justin Stanford Davis received his Ph.D. in Electrical Engineering from the Georgia Institute of Technology in August 2003, as well as his M.S. and B.E.E. degrees in 1999 and 1997. During the summers of 1998 and 1999, he worked at Hewlett-Packard (now Agilent Technologies). In fall of 2003, he joined the faculty in the Department of Electrical Engineering at Mississippi State University as an Assistant Professor. His research interests include digital testing for high-speed systems, SoCs, and SoPs, as well as signal integrity, systems engineering, and faulttolerant design. He is currently working on the development of low-cost test support processors using programmable devices.

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